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| NAIBRDFUNC nai_status_t NAIAPI | naibrd_SUM1553_SetInterruptMask (int32_t cardIndex, int32_t module, int32_t channel, nai_sum1553_interrupt_t mask) |
| | Sets the Interrupt Mask (Core Register 3). An interrupt is masked if the corresponding bit of this register is set to low, allowing the host or subsystem to temporarily disable the service of interrupts. While masked, interrupt notification does not occur. The unmasking of an interrupt after the event occurs does not generate an interrupt for that event.
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| NAIBRDFUNC nai_status_t NAIAPI | naibrd_SUM1553_SetInterruptVector (int32_t cardIndex, int32_t module, int32_t channel, uint32_t vector) |
| | Sets the Interrupt Vector for the specified 1553 channel.
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| NAIBRDFUNC nai_status_t NAIAPI | naibrd_SUM1553_GetInterruptVector (int32_t cardIndex, int32_t module, int32_t channel, uint32_t *outvector) |
| | Gets the Interrupt Vector for the specified 1553 channel.
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| NAIBRDFUNC nai_status_t NAIAPI | naibrd_SUM1553_GetInterruptStatus (int32_t cardIndex, int32_t module, int32_t channel, nai_sum1553_interrupt_t *outpending) |
| | Retrieves the data in the Pending Interrupt register (Core Register 4). This register identifies interrupt events. The Pending Interrupt register is cleared at the end of a read or write to any other core register.
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| NAIBRDFUNC nai_status_t NAIAPI | naibrd_SUM1553_GetInterruptLogPtr (int32_t cardIndex, int32_t module, int32_t channel, uint16_t *outaddr) |
| | Retrieves the data in the Interrupt Pointer register (Core Register 5). The Interrupt Pointer register contains the starting base address and pointer location of the Interrupt Log List. The Interrupt Log List is a 32-word ring-buffer that contains information necessary to service interrupts. The most significant 11 bits designate the base address of the ring buffer (which occurs on a 32-word boundary, i.e., the host must initialize the five least significant bits). Note the naibrd_SUM1553_SetMode() routine initializes Interrupt Pointer register to 0xF000. The core controls the five least significant bits to indicate the pointer location. The host or subsystem reads these five bits to determine the location and number of interrupts within the Interrupt Log List.
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| NAIBRDFUNC nai_status_t NAIAPI | naibrd_SUM1553_GetInterruptLogEntry (int32_t cardIndex, int32_t module, int32_t channel, uint16_t addr, uint16_t *outstatus, uint16_t *outaddr) |
| | Retrieves the Interrupt Information Word (IIW) and Interrupt Address Word (IAW) associated with the Interrupt Log List Address. The Interrupt Information Word format is identical to that of the Pending Interrupt register (Core Register 4).
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| NAIBRDFUNC nai_status_t NAIAPI | naibrd_SUM1553_InstallLogIDR (int32_t cardIndex, int32_t module, int32_t channel, int32_t slot, nai_ether_upr_type_t uprtype, uint8_t ip[], uint16_t port, uint8_t seqhi, uint16_t vector) |
| | Sets up a Interrupt Driven Reply (IDR) Unprompted Reply (UPR) that will read the Interrupt Pending Register (Core Register 4) whenever the interrupt associated with the vector passed in occurs.
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| NAIBRDFUNC nai_status_t NAIAPI | naibrd_SUM1553_ProcessLogIDR (int32_t cardIndex, int32_t module, int32_t channel, uint8_t msg[], nai_ether_typecode_t typecode, nai_ether_gen_t gen, int32_t offset, uint16_t *outlogptr) |
| | Decodes the UPR Read message that is passed in and returns the data content.
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| NAIBRDFUNC nai_status_t NAIAPI naibrd_SUM1553_GetInterruptStatus |
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int32_t | cardIndex, |
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int32_t | module, |
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int32_t | channel, |
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nai_sum1553_interrupt_t * | outpending ) |
Retrieves the data in the Pending Interrupt register (Core Register 4). This register identifies interrupt events. The Pending Interrupt register is cleared at the end of a read or write to any other core register.
The following interrupts events are monitored:
- DMA Fail Interrupt (DMAF) (bit 15) - For all operating modes: to allow the core to correctly transmit and
receive on the 1553 bus, all memory accesses must complete within a specified time. When the core accesses
memory, an internal timer is started. If the memory access is not completed by the time the counter decrements
to 0, this interrupt is generated. If DMAF occurs, current command processing ends, and the core will remain
on-line. During RT operation, the current cycle terminates, and the bus is released.
- Wrap Fail Interrupt (WRAPF) (bit 14) - For BC and RT modes only: the core automatically compares the
transmitted word (encoder word) to the reflected decoder word via the continuous loopback feature. If the
encoder word and reflected word do not match, the WRAPF bit is set.
- Terminal Address Parity Fail Interrupt (TAPF) (bit 13) - For RT mode only: this bit is set high to indicate
an RT address parity error. When a parity error occurs, the core will not begin operation (Control Register
Start Execution (STEX) bit (Core Register 0 bit 15) is forced low and Bus A and Bus B are not enabled.
- Message Error Interrupt (MERR) (bit 11) - For all operating modes: if the core detects errors in Manchester,
sync-field, word count (too many or too few), MIL-STD-1553 word parity, bit count (too many or too few), or
protocol errors, this bit will be set. During RT operation, this bit is always set for illegal commands, invalid
data word, etc.
- Subaddress Accessed Interrupt (SUBAD) (bit 10) - For RT operating mode only: this bit is set when a pre-selected
subaddress has transacted a message. To pre-select a sub-address, the Interrupt when Accessed (IWA) bit (bit 6)
in the subaddress descriptor block control word is set. The host must query the interrupt log Interrupt Address
Word (IAW) to determine which subaddress generated the interrupt.
- Broadcast Command Received Interrupt (BDRCV) (bit 9) - For RT operating mode only: when the core receives a valid
broadcast command, BDRCV is set and the core suppresses status word transmission.
- Index Equal Zero Interrupt (IXEQ0) (bit 8) - For RT operating mode only: the core sets the IXEQ0 to indicate the
completion of a predefined number of commands by the core. This interrupt is generated in the INDEX mode when the
INDX (bits 15:8) value in the subaddress descriptor block control word decrements from 1 to 0 or when in Circular
Buffer mode a buffer wraps back to the start. When this interrupt occurs, the host or subsystem must update the
subaddress descriptor block to prevent potential loss of data.
- Illegal Command Interrupt (ILLCMD) (bit 7) - For RT operating mode only: when the core receives an illegal command,
ILLCMD is set and responds with a status word only. Bit 9 of the status word is set. A command is determined legal
or illegal by the legalization registers (Core Registers 16 to 31).
- End of List Interrupt (EOL) (bit 5) - For BC operating mode only: this bit is set when the core reaches the End of
List command.
- Illogical Command Interrupt (ILLCMD) (bit 4) - For BC operating mode only: the core checks for RT-RT terminal address
field match, RT-RT transmit/receive bit mismatch and correct order, and broadcase transmit commands. When an error
is detected, the core sets this bit and will halt execution.
- Illogical Opcode Interrupt (ILLOP) (bit 3) - For BC operating mode only: if a reserved opcode occurs in a command
block, the core will set this bit and halt operation.
- Retry Fail Interrupt (RTF) (bit 2) - For BC operating mode only: the core sets this bit when all programmed retries
have failed.
- Command Block Accessed Interrupt (bit 1) - For BC operating mode only: the core sets this bit when a command block
is accessed with the Interrupt-Continue opcode (1010b). This opcode instructs the core to generate an interrupt and
continue with the next command block.
- Monitor Block Counter Interrupt (bit 0) - For BM operating mode only: when the core's monitor block counter reaches
0, this bit is set. Note, the core does not discriminate between messages with or without errors.
- Parameters
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| cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
| module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
| channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
| outpending | : (Output) Pending Interrupt Events. |
- Returns
- NAI_SUCCESS
- NAI_ERROR_INVALID_CARD when invalid card parameter is specified.
- NAI_ERROR_INVALID_MODULE when invalid card parameter is specified.
- NAI_ERROR_NOT_OPEN when handle to board is invalid.
- NAI_ERROR_INVALID_CHANNEL when invalid channel parameter is specified.
- NAI_ERROR_NOT_SUPPORTED when function is not supported.
| NAIBRDFUNC nai_status_t NAIAPI naibrd_SUM1553_SetInterruptMask |
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int32_t | cardIndex, |
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int32_t | module, |
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int32_t | channel, |
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nai_sum1553_interrupt_t | mask ) |
Sets the Interrupt Mask (Core Register 3). An interrupt is masked if the corresponding bit of this register is set to low, allowing the host or subsystem to temporarily disable the service of interrupts. While masked, interrupt notification does not occur. The unmasking of an interrupt after the event occurs does not generate an interrupt for that event.
The following interrupts can be masked:
- DMA Fail Interrupt (DMAF) (bit 15) - For all operating modes: to allow the core to correctly transmit and
receive on the 1553 bus, all memory accesses must complete within a specified time. When the core accesses
memory, an internal timer is started. If the memory access is not completed by the time the counter decrements
to 0, this interrupt is generated. If DMAF occurs, current command processing ends, and the core will remain
on-line. During RT operation, the current cycle terminates, and the bus is released.
- Wrap Fail Interrupt (WRAPF) (bit 14) - For BC and RT modes only: the core automatically compares the
transmitted word (encoder word) to the reflected decoder word via the continuous loopback feature. If the
encoder word and reflected word do not match, the WRAPF bit is set.
- Terminal Address Parity Fail Interrupt (TAPF) (bit 13) - For RT mode only: this bit is set high to indicate
an RT address parity error. When a parity error occurs, the core will not begin operation (Control Register
Start Execution (STEX) bit (Core Register 0 bit 15) is forced low and Bus A and Bus B are not enabled.
- Message Error Interrupt (MERR) (bit 11) - For all operating modes: if the core detects errors in Manchester,
sync-field, word count (too many or too few), MIL-STD-1553 word parity, bit count (too many or too few), or
protocol errors, this bit will be set. During RT operation, this bit is always set for illegal commands, invalid
data word, etc.
- Subaddress Accessed Interrupt (SUBAD) (bit 10) - For RT operating mode only: this bit is set when a pre-selected
subaddress has transacted a message. To pre-select a sub-address, the Interrupt when Accessed (IWA) bit (bit 6)
in the subaddress descriptor block control word is set. The host must query the interrupt log Interrupt Address
Word (IAW) to determine which subaddress generated the interrupt.
- Broadcast Command Received Interrupt (BDRCV) (bit 9) - For RT operating mode only: when the core receives a valid
broadcast command, BDRCV is set and the core suppresses status word transmission.
- Index Equal Zero Interrupt (IXEQ0) (bit 8) - For RT operating mode only: the core sets the IXEQ0 to indicate the
completion of a predefined number of commands by the core. This interrupt is generated in the INDEX mode when the
INDX (bits 15:8) value in the subaddress descriptor block control word decrements from 1 to 0 or when in Circular
Buffer mode a buffer wraps back to the start. When this interrupt occurs, the host or subsystem must update the
subaddress descriptor block to prevent potential loss of data.
- Illegal Command Interrupt (ILLCMD) (bit 7) - For RT operating mode only: when the core receives an illegal command,
ILLCMD is set and responds with a status word only. Bit 9 of the status word is set. A command is determined legal
or illegal by the legalization registers (Core Registers 16 to 31).
- End of List Interrupt (EOL) (bit 5) - For BC operating mode only: this bit is set when the core reaches the End of
List command.
- Illogical Command Interrupt (ILLCMD) (bit 4) - For BC operating mode only: the core checks for RT-RT terminal address
field match, RT-RT transmit/receive bit mismatch and correct order, and broadcase transmit commands. When an error
is detected, the core sets this bit and will halt execution.
- Illogical Opcode Interrupt (ILLOP) (bit 3) - For BC operating mode only: if a reserved opcode occurs in a command
block, the core will set this bit and halt operation.
- Retry Fail Interrupt (RTF) (bit 2) - For BC operating mode only: the core sets this bit when all programmed retries
have failed.
- Command Block Accessed Interrupt (bit 1) - For BC operating mode only: the core sets this bit when a command block
is accessed with the Interrupt-Continue opcode (1010b). This opcode instructs the core to generate an interrupt and
continue with the next command block.
- Monitor Block Counter Interrupt (bit 0) - For BM operating mode only: when the core's monitor block counter reaches
0, this bit is set. Note, the core does not discriminate between messages with or without errors.
- Parameters
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| cardIndex | : (Input) Logical Card Index assigned to connection with the NAI_BOARD (0 - NAI_MAX_CARDS-1). |
| module | : (Input) Module Number of the module to access (1 - [max modules for board]). |
| channel | : (Input) Channel Number of the channel to access (1 - [max channels for module]). |
| mask | : (Input) Interrupt mask. |
- Returns
- NAI_SUCCESS
- NAI_ERROR_INVALID_CARD when invalid card parameter is specified.
- NAI_ERROR_INVALID_MODULE when invalid card parameter is specified.
- NAI_ERROR_NOT_OPEN when handle to board is invalid.
- NAI_ERROR_INVALID_CHANNEL when invalid channel parameter is specified.
- NAI_ERROR_NOT_SUPPORTED when function is not supported.
1.11.0