N7/N8 (Summit) 1553 Module Functions

Topics
	Module Properties Functions
	Bus Controller/Remote Terminal/Bus Monitor Functions
	Bus Controller Specific Functions
	Remote Terminal Specific Functions
	Bus Monitor Specific Functions
	Interrupt Specific Functions
	Core Memory Access Functions
	Processor Controlled RT Functions

Detailed Description

N7/N8 1553 Core

The N7 and N8 1553 Module uses Actel's Core1553BRM. The Core1553BRM provides a complete, MIL-STD-1553B bus controller (BC), remote terminal (RT) or bus monitor terminal (BM or MT). The Core1553BRM is software- compatible with the UTMC 69151 (Summit) 1553 device.

Regardless of whether the Core1553BRM is used to implement a BC, RT, or BM, functionality of the core is controlled via core register configuration. There are 33 core register, of which 17 are used for control functions and 16 for RT command illegalization. Use of the RT command illegalization registers is optional.

Register	Register Name	RT	BC	BM
00	Control	X	X	X
01	Operation and Status	X	X	X
02	Current Command	X	X	X
03	Interrupt Mask	X	X	X
04	Pending Interrupt	X	X	X
05	Interrupt Pointer	X	X	X
06	Built-In-Test Register	X	X	X
07	Time Tag/Minor Frame Timer	X	X	X
08	Descriptor/Command Block Pointer	X	X
09	1553A/B Status Word	X
10	Initialization Count
11	Monitor Command Pointer			X
12	Monitor Data Pointer			X
13	Monitor Block Count			X
14	Monitor Filter A			X
15	Monitor Filter B			X
16-31	RT Illegalization Registers	X
32	Enhanced Features	X	X	X

Refer to the Actel Core 1553 Handbook for additional information about the Core1553BRM.

N7/N8 Interrupts

The Core1553BRM incorporates an interrupt system to allow the host or subsystem to correctly identify the type of interrupt that has occurred as well as determine its cause. Interrupts are broken into two classes: hardware and message interrupts. Hardware interrupts need to be serviced as soon as they occur, while message interrupts are stored for later investigation.

All interrupts are stored in the Pending Interrupt register (Core Register 4), depending on the settings of the Interrupt Mask register (Core Register 3). The most significant four bits are classed as hardware interrupts, the lower bits as message interrupts. When a hardware interrupt occurs, the core will set the appropriate bit in the Pending Interrupt register. When alerted, the host or subsystem should service the interrupt immediately as hardware interrupts are not stored by the core, and until the interrupt is cleared no further hardware interrupt will be signaled.

When a message interrupt occurs, the core will set the appropriate bit in the Pending Interrupt register. If enabled, these interrupts are also stored in the Interrupt Log List, a 32-ring buffer. Each interrupt is stored using two words of information:

• Interrupt Information Word (IIW) - a 16-bit word with format identical to that of the Pending Interrupt register with the four most significant bits masked.
• Interrupt Address Word (IAW) - a 16-bit word that identifies the source of the interrupt (content varies with core mode (BC, RT, or BM) configuration).

With each message interrupt, the system will store the interrupt in the Interrupt Log List based on the Interrupt Pointer register (Core Register 5) with the first IIW stored at address offset 0, the first IAW stored at address offset 1 and so on until the ubffer wraps while storing the 17th message interrupt (the core updates the value of the least-significant five bits of the Interrupt Pointer register while storing each interrupt word).

N7/N8 Processor Controlled RT Mode

If the NAI_SUM1553_PROC_CTRL_ENABLE is enabled (1), the 1553 Module Processor will take over the control the Remote Terminal handling of 1553 messages and requests. Using the 1553 Interrupt mechanism, the Processor will place any received 1553 messages on the "Event" FIFO. If using Ethernet communication, the host or subsystem needs to setup the "Unprompted Reply" (UPR) for Interrupt Driven Reply (IDR) Ethernet message so that the data in the "Event" FIFO is automatically sent to the host or subsystem. For applications that want to use the Processor Controlled mechanism and do not use the IDR Ethernet mechanism, it is important to make sure that the "Event" FIFO does not become full which will result in lost 1553 messages.

When in 1553 Processor controlled mode, updates to the Core memory must be done via request on the "Request" FIFO and responses are placed in the "Response" FIFO. Note, while in Processor controlled mode, the host should not access the Core memory directly. Doing so may result in changing the value of the "page" register resulting in unpredictable behavior. If the NAI_SUM1553_PROC_CTRL_HPRIOREQ is enabled (1), the requests will have higher priority than the 1553 message interrupts.